Product Profile of Packet-switched Physical Layer Interface Core
Silicon Interfaces Pvt. Ltd. offers Packet-switched Physical Layer Interface Core. Silicon Interfaces Pvt. Ltd. supplies solutions and services in the technology segment and as a technology-facilitator for retail, banking, financial, telecom, travel and trade segment for internet, applications and the enterprise using Microsoft, J2EE and IBM technologies on Microsoft Operating Systems and UNIX on Intel compatible and other processor platforms. Packet-switched Physical Layer Interface Core is a packet-switched interconnect intended primarily as an intra-system interfaces for a chip-to-chip and board-to-board communications at Gigabyte-per-second performance levels. Packet-switched Physical Layer Interface Core is focused as a processor, memory and memory mapped I/O interfaces optimized for use inside the chassis.
Key Features of Packet-switched Physical Layer Interface Core
- 32-bit standard Host/Link Interface.
- Full Duplex Independent Transmit and Receive Data Path.
- Dual Data Rate [DDR]: 62.5-125 MHz.
- Auto scaling 8/16 bit Ports.
- Respects 32-bit boundaries.
- Rx Queuing: 16 X 128 X 32 or 8 Kbytes of internal buffer.
- Tx Queuing: 8 X 128 X 32 or 4 Kbytes of internal buffer.
- Maximum Packet Length: 276 bytes.
- Minimum Packet Length: 8 bytes.
